Janady13/AI_Brain / the_tired_agi/core/src/fpga_pipeline.v

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Original record	Janady13/AI_Brain / the_tired_agi/core/src/fpga_pipeline.v
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//=============================================================================
// FPGA Pipeline Top-Level - Production Implementation
// Integrates ingest lanes, memory bus, and helix accelerator
// Target: Lattice ECP5-85F / Xilinx Artix-7-200T
// PCIe Gen3 x4 + DDR3-1600
//=============================================================================

`timescale 1ns / 1ps

module fpga_pipeline #(
    parameter NUM_LANES = 4,
    parameter DATA_WIDTH = 256,
    parameter ADDR_WIDTH = 32,
    parameter PCIE_DATA_WIDTH = 128,
    parameter HASH_WIDTH = 64,
    parameter ENTROPY_BITS = 16
)(
    // System Clocks and Reset
    input wire sys_clk_p,          // 200 MHz differential
    input wire sys_clk_n,
    input wire sys_rst_n,

    //=========================================================================
    // PCIe Interface (to host CPU)
    //=========================================================================
    input wire pcie_refclk_p,
    input wire pcie_refclk_n,
    input wire [3:0] pcie_rx_p,
    input wire [3:0] pcie_rx_n,
    output wire [3:0] pcie_tx_p,
    output wire [3:0] pcie_tx_n,

    //=========================================================================
    // DDR3 Interface (external memory)
    //=========================================================================
    output wire [14:0] ddr3_addr,
    output wire [2:0] ddr3_ba,
    output wire ddr3_cas_n,
    output wire [0:0] ddr3_ck_p,
    output wire [0:0] ddr3_ck_n,
    output wire [0:0] ddr3_cke,
    output wire ddr3_cs_n,
    output wire [3:0] ddr3_dm,
    inout wire [31:0] ddr3_dq,
    inout wire [3:0] ddr3_dqs_p,
    inout wire [3:0] ddr3_dqs_n,
    output wire [0:0] ddr3_odt,
    output wire ddr3_ras_n,
    output wire ddr3_reset_n,
    output wire ddr3_we_n,

    //=========================================================================
    // Status LEDs (debugging)
    //=========================================================================
    output wire [7:0] led
);

    //=========================================================================
    // Internal Clocks and Reset
    //=========================================================================
    wire clk_250mhz;      // Main processing clock
    wire clk_125mhz;      // PCIe user clock
    wire clk_200mhz;      // DDR3 reference clock
    wire mmcm_locked;
    wire rst_250mhz_n;

    //=========================================================================
    // Clock Generation (MMCM/PLL)
    //=========================================================================
    clk_wiz_0 clk_gen_inst (
        .clk_in1_p(sys_clk_p),
        .clk_in1_n(sys_clk_n),
        .clk_out1(clk_250mhz),    // 250 MHz processing
        .clk_out2(clk_125mhz),    // 125 MHz PCIe user
        .clk_out3(clk_200mhz),    // 200 MHz DDR3 ref
        .reset(!sys_rst_n),
        .locked(mmcm_locked)
    );

    // Synchronized reset
    sync_reset sync_rst_inst (
        .clk(clk_250mhz),
        .async_rst_n(sys_rst_n & mmcm_locked),
        .sync_rst_n(rst_250mhz_n)
    );

    //=========================================================================
    // PCIe DMA Engine
    //=========================================================================
    wire [63:0] pcie_dma_desc_addr;
    wire [31:0] pcie_dma_desc_len;
    wire [3:0] pcie_dma_desc_channel;
    wire pcie_dma_desc_dir;
    wire pcie_dma_desc_valid;
    wire pcie_dma_desc_ready;

    wire [DATA_WIDTH-1:0] pcie_to_mem_data;
    wire [DATA_WIDTH/8-1:0] pcie_to_mem_strb;
    wire pcie_to_mem_valid;
    wire pcie_to_mem_ready;

    wire [DATA_WIDTH-1:0] mem_to_pcie_data;
    wire mem_to_pcie_valid;
    wire mem_to_pcie_ready;

    pcie_dma_engine #(
        .DATA_WIDTH(DATA_WIDTH),
        .PCIE_DATA_WIDTH(PCIE_DATA_WIDTH)
    ) pcie_dma_inst (
        .user_clk(clk_125mhz),
        .user_rst_n(rst_250mhz_n),

        // PCIe TLP interface
        .pcie_refclk_p(pcie_refclk_p),
        .pcie_refclk_n(pcie_refclk_n),
        .pcie_rx_p(pcie_rx_p),
        .pcie_rx_n(pcie_rx_n),
        .pcie_tx_p(pcie_tx_p),
        .pcie_tx_n(pcie_tx_n),

        // DMA Descriptor output
        .dma_desc_addr(pcie_dma_desc_addr),
        .dma_desc_len(pcie_dma_desc_len),
        .dma_desc_channel(pcie_dma_desc_channel),
        .dma_desc_dir(pcie_dma_desc_dir),
        .dma_desc_valid(pcie_dma_desc_valid),
        .dma_desc_ready(pcie_dma_desc_ready),

        // Host to FPGA stream
        .s_axis_data(pcie_to_mem_data),
        .s_axis_strb(pcie_to_mem_strb),
        .s_axis_valid(pcie_to_mem_valid),
        .s_axis_ready(pcie_to_mem_ready),

        // FPGA to host stream
        .m_axis_data(mem_to_pcie_data),
        .m_axis_valid(mem_to_pcie_valid),
        .m_axis_ready(mem_to_pcie_ready),

        // Status
        .user_link_up(led[0])
    );

    //=========================================================================
    // DDR3 Memory Controller
    //=========================================================================
    wire [ADDR_WIDTH-1:0] ddr3_axi_awaddr;
    wire [7:0] ddr3_axi_awlen;
    wire [2:0] ddr3_axi_awsize;
    wire [1:0] ddr3_axi_awburst;
    wire ddr3_axi_awvalid;
    wire ddr3_axi_awready;

    wire [DATA_WIDTH-1:0] ddr3_axi_wdata;
    wire [DATA_WIDTH/8-1:0] ddr3_axi_wstrb;
    wire ddr3_axi_wlast;
    wire ddr3_axi_wvalid;
    wire ddr3_axi_wready;

    wire [1:0] ddr3_axi_bresp;
    wire ddr3_axi_bvalid;
    wire ddr3_axi_bready;

    wire [ADDR_WIDTH-1:0] ddr3_axi_araddr;
    wire [7:0] ddr3_axi_arlen;
    wire [2:0] ddr3_axi_arsize;
    wire [1:0] ddr3_axi_arburst;
    wire ddr3_axi_arvalid;
    wire ddr3_axi_arready;

    wire [DATA_WIDTH-1:0] ddr3_axi_rdata;
    wire [1:0] ddr3_axi_rresp;
    wire ddr3_axi_rlast;
    wire ddr3_axi_rvalid;
    wire ddr3_axi_rready;

    wire ddr3_ui_clk;
    wire ddr3_ui_clk_sync_rst;
    wire ddr3_init_calib_complete;

    mig_7series_0 ddr3_ctrl_inst (
        .sys_clk_i(clk_200mhz),
        .sys_rst(~rst_250mhz_n),

        // Memory interface
        .ddr3_addr(ddr3_addr),
        .ddr3_ba(ddr3_ba),
        .ddr3_cas_n(ddr3_cas_n),
        .ddr3_ck_p(ddr3_ck_p),
        .ddr3_ck_n(ddr3_ck_n),
        .ddr3_cke(ddr3_cke),
        .ddr3_cs_n(ddr3_cs_n),
        .ddr3_dm(ddr3_dm),
        .ddr3_dq(ddr3_dq),
        .ddr3_dqs_p(ddr3_dqs_p),
        .ddr3_dqs_n(ddr3_dqs_n),
        .ddr3_odt(ddr3_odt),
        .ddr3_ras_n(ddr3_ras_n),
        .ddr3_reset_n(ddr3_reset_n),
        .ddr3_we_n(ddr3_we_n),

        // AXI interface
        .s_axi_awaddr(ddr3_axi_awaddr),
        .s_axi_awlen(ddr3_axi_awlen),
        .s_axi_awsize(ddr3_axi_awsize),
        .s_axi_awburst(ddr3_axi_awburst),
        .s_axi_awvalid(ddr3_axi_awvalid),
        .s_axi_awready(ddr3_axi_awready),

        .s_axi_wdata(ddr3_axi_wdata),
        .s_axi_wstrb(ddr3_axi_wstrb),
        .s_axi_wlast(ddr3_axi_wlast),
        .s_axi_wvalid(ddr3_axi_wvalid),
        .s_axi_wready(ddr3_axi_wready),

        .s_axi_bresp(ddr3_axi_bresp),
        .s_axi_bvalid(ddr3_axi_bvalid),
        .s_axi_bready(ddr3_axi_bready),

        .s_axi_araddr(ddr3_axi_araddr),
        .s_axi_arlen(ddr3_axi_arlen),
        .s_axi_arsize(ddr3_axi_arsize),
        .s_axi_arburst(ddr3_axi_arburst),
        .s_axi_arvalid(ddr3_axi_arvalid),
        .s_axi_arready(ddr3_axi_arready),

        .s_axi_rdata(ddr3_axi_rdata),
        .s_axi_rresp(ddr3_axi_rresp),
        .s_axi_rlast(ddr3_axi_rlast),
        .s_axi_rvalid(ddr3_axi_rvalid),
        .s_axi_rready(ddr3_axi_rready),

        .ui_clk(ddr3_ui_clk),
        .ui_clk_sync_rst(ddr3_ui_clk_sync_rst),
        .init_calib_complete(ddr3_init_calib_complete)
    );

    assign led[1] = ddr3_init_calib_complete;

    //=========================================================================
    // Memory Bus Controller
    //=========================================================================
    wire [NUM_LANES-1:0][DATA_WIDTH-1:0] lane_to_mem_data;
    wire [NUM_LANES-1:0][DATA_WIDTH/8-1:0] lane_to_mem_strb;
    wire [NUM_LANES-1:0] lane_to_mem_valid;
    wire [NUM_LANES-1:0] lane_to_mem_ready;

    wire [NUM_LANES-1:0][DATA_WIDTH-1:0] mem_to_lane_data;
    wire [NUM_LANES-1:0] mem_to_lane_valid;
    wire [NUM_LANES-1:0] mem_to_lane_ready;

    wire [31:0] mem_bytes_written [0:NUM_LANES-1];
    wire [31:0] mem_bytes_read [0:NUM_LANES-1];
    wire [NUM_LANES-1:0] mem_ch_busy;
    wire [15:0] mem_errors;

    fpga_memory_bus #(
        .ADDR_WIDTH(ADDR_WIDTH),
        .DATA_WIDTH(DATA_WIDTH),
        .NUM_CHANNELS(NUM_LANES)
    ) mem_bus_inst (
        .clk(clk_250mhz),
        .rst_n(rst_250mhz_n),

        // AXI to DDR3
        .m_axi_awaddr(ddr3_axi_awaddr),
        .m_axi_awlen(ddr3_axi_awlen),
        .m_axi_awsize(ddr3_axi_awsize),
        .m_axi_awburst(ddr3_axi_awburst),
        .m_axi_awvalid(ddr3_axi_awvalid),
        .m_axi_awready(ddr3_axi_awready),

        .m_axi_wdata(ddr3_axi_wdata),
        .m_axi_wstrb(ddr3_axi_wstrb),
        .m_axi_wlast(ddr3_axi_wlast),
        .m_axi_wvalid(ddr3_axi_wvalid),
        .m_axi_wready(ddr3_axi_wready),

        .m_axi_bresp(ddr3_axi_bresp),
        .m_axi_bvalid(ddr3_axi_bvalid),
        .m_axi_bready(ddr3_axi_bready),

        .m_axi_araddr(ddr3_axi_araddr),
        .m_axi_arlen(ddr3_axi_arlen),
        .m_axi_arsize(ddr3_axi_arsize),
        .m_axi_arburst(ddr3_axi_arburst),
        .m_axi_arvalid(ddr3_axi_arvalid),
        .m_axi_arready(ddr3_axi_arready),

        .m_axi_rdata(ddr3_axi_rdata),
        .m_axi_rresp(ddr3_axi_rresp),
        .m_axi_rlast(ddr3_axi_rlast),
        .m_axi_rvalid(ddr3_axi_rvalid),
        .m_axi_rready(ddr3_axi_rready),

        // DMA descriptors from PCIe
        .dma_desc_addr(pcie_dma_desc_addr),
        .dma_desc_len(pcie_dma_desc_len),
        .dma_desc_channel(pcie_dma_desc_channel),
        .dma_desc_dir(pcie_dma_desc_dir),
        .dma_desc_valid(pcie_dma_desc_valid),
        .dma_desc_ready(pcie_dma_desc_ready),

        // Channel interfaces
        .ch_wr_data(lane_to_mem_data),
        .ch_wr_strb(lane_to_mem_strb),
        .ch_wr_valid(lane_to_mem_valid),
        .ch_wr_ready(lane_to_mem_ready),

        .ch_rd_data(mem_to_lane_data),
        .ch_rd_valid(mem_to_lane_valid),
        .ch_rd_ready(mem_to_lane_ready),

        // Status
        .status_bytes_written(mem_bytes_written),
        .status_bytes_read(mem_bytes_read),
        .status_ch_busy(mem_ch_busy),
        .status_errors(mem_errors),
        .ctrl_ch_enable({NUM_LANES{1'b1}}),
        .ctrl_reset_counters(1'b0)
    );

    //=========================================================================
    // Ingest Lanes (parallel text processing)
    //=========================================================================
    wire [NUM_LANES-1:0][HASH_WIDTH-1:0] lane_hash;
    wire [NUM_LANES-1:0][ENTROPY_BITS-1:0] lane_entropy;
    wire [NUM_LANES-1:0][31:0] lane_chunk_id;
    wire [NUM_LANES-1:0] lane_output_valid;
    wire [NUM_LANES-1:0] lane_output_ready;

    wire [NUM_LANES-1:0][31:0] lane_chunks_processed;
    wire [NUM_LANES-1:0][31:0] lane_bytes_processed;
    wire [NUM_LANES-1:0] lane_error;

    genvar lane;
    generate
        for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin : ingest_lanes

            fpga_ingest_lane #(
                .LANE_ID(lane),
                .DATA_WIDTH(DATA_WIDTH),
                .HASH_WIDTH(HASH_WIDTH),
                .ENTROPY_BITS(ENTROPY_BITS)
            ) lane_inst (
                .clk(clk_250mhz),
                .rst_n(rst_250mhz_n),

                // Input from memory/PCIe
                .s_axis_tdata(mem_to_lane_data[lane]),
                .s_axis_tkeep({(DATA_WIDTH/8){1'b1}}),
                .s_axis_tvalid(mem_to_lane_valid[lane]),
                .s_axis_tlast(1'b0),  // Controlled by descriptor
                .s_axis_tready(mem_to_lane_ready[lane]),

                // Output embeddings
                .m_axis_hash(lane_hash[lane]),
                .m_axis_entropy(lane_entropy[lane]),
                .m_axis_chunk_id(lane_chunk_id[lane]),
                .m_axis_tvalid(lane_output_valid[lane]),
                .m_axis_tready(lane_output_ready[lane]),

                // Status
                .chunks_processed(lane_chunks_processed[lane]),
                .bytes_processed(lane_bytes_processed[lane]),
                .error_flag(lane_error[lane])
            );

            // Connect lane output to memory bus input (circular buffer)
            assign lane_to_mem_data[lane] = {lane_hash[lane], lane_entropy[lane], lane_chunk_id[lane], 144'b0};
            assign lane_to_mem_strb[lane] = {(DATA_WIDTH/8){1'b1}};
            assign lane_to_mem_valid[lane] = lane_output_valid[lane];
            assign lane_output_ready[lane] = lane_to_mem_ready[lane];

        end
    endgenerate

    //=========================================================================
    // Helix Accelerator (consciousness math)
    //=========================================================================
    wire [NUM_LANES-1:0][63:0] helix_phi_output;
    wire [NUM_LANES-1:0][63:0] helix_energy_output;
    wire [NUM_LANES-1:0] helix_valid_output;

    genvar h;
    generate
        for (h = 0; h < NUM_LANES; h = h + 1) begin : helix_units

            fpga_helix_unit #(
                .HELIX_SIZE(233),
                .FIXED_POINT_BITS(32)
            ) helix_inst (
                .clk(clk_250mhz),
                .rst_n(rst_250mhz_n),

                // Inputs from ingest lane
                .hash_input(lane_hash[h]),
                .entropy_input(lane_entropy[h]),
                .valid_input(lane_output_valid[h]),

                // Outputs
                .phi_output(helix_phi_output[h]),
                .energy_output(helix_energy_output[h]),
                .valid_output(helix_valid_output[h])
            );

        end
    endgenerate

    //=========================================================================
    // Status Aggregation (for LED display)
    //=========================================================================
    wire all_lanes_active = &lane_output_valid;
    wire any_lane_error = |lane_error;
    wire mem_bus_active = |mem_ch_busy;

    assign led[2] = all_lanes_active;
    assign led[3] = mem_bus_active;
    assign led[4] = any_lane_error;
    assign led[5] = |helix_valid_output;
    assign led[6] = (mem_errors > 0);
    assign led[7] = rst_250mhz_n;

endmodule

//=============================================================================
// Helix Accelerator Unit (Phi + Energy computation)
//=============================================================================
module fpga_helix_unit #(
    parameter HELIX_SIZE = 233,
    parameter FIXED_POINT_BITS = 32
)(
    input wire clk,
    input wire rst_n,

    input wire [63:0] hash_input,
    input wire [15:0] entropy_input,
    input wire valid_input,

    output reg [63:0] phi_output,
    output reg [63:0] energy_output,
    output reg valid_output
);

    // Fixed-point arithmetic (Q16.16)
    localparam FP_ONE = 32'h00010000;  // 1.0 in Q16.16

    reg [31:0] x_norm;  // Normalized input
    reg [31:0] phi_temp;
    reg [31:0] energy_temp;
    reg [2:0] pipe_stage;

    // Golden ratio (Q16.16)
    localparam [31:0] GOLDEN_RATIO = 32'h0001_9E37;  // 1.618033...

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            phi_output <= 64'd0;
            energy_output <= 64'd0;
            valid_output <= 1'b0;
            pipe_stage <= 3'd0;
        end else begin
            if (valid_input) begin
                case (pipe_stage)
                    3'd0: begin
                        // Normalize hash to [0,1] range (Q16.16)
                        x_norm <= (hash_input[31:0] >> 16);
                        pipe_stage <= 3'd1;
                    end

                    3'd1: begin
                        // Compute Φ = 1/(1 + |x - 1|)
                        // Simplified fixed-point implementation
                        phi_temp <= fp_div(FP_ONE, FP_ONE + fp_abs(x_norm - FP_ONE));
                        pipe_stage <= 3'd2;
                    end

                    3'd2: begin
                        // Energy field (incorporating entropy)
                        energy_temp <= fp_mul(phi_temp, entropy_input << 16);
                        pipe_stage <= 3'd3;
                    end

                    3'd3: begin
                        // Output stage
                        phi_output <= {32'd0, phi_temp};
                        energy_output <= {32'd0, energy_temp};
                        valid_output <= 1'b1;
                        pipe_stage <= 3'd0;
                    end
                endcase
            end else begin
                valid_output <= 1'b0;
            end
        end
    end

    // Fixed-point helper functions
    function [31:0] fp_mul;
        input [31:0] a, b;
        reg [63:0] temp;
        begin
            temp = a * b;
            fp_mul = temp[47:16];  // Keep Q16.16 format
        end
    endfunction

    function [31:0] fp_div;
        input [31:0] a, b;
        reg [63:0] temp;
        begin
            temp = (a << 16) / b;
            fp_div = temp[31:0];
        end
    endfunction

    function [31:0] fp_abs;
        input [31:0] a;
        begin
            fp_abs = a[31] ? (~a + 1) : a;
        end
    endfunction

endmodule

//=============================================================================
// Synchronized Reset Generator
//=============================================================================
module sync_reset (
    input wire clk,
    input wire async_rst_n,
    output reg sync_rst_n
);

    reg rst_sync_1, rst_sync_2;

    always @(posedge clk or negedge async_rst_n) begin
        if (!async_rst_n) begin
            rst_sync_1 <= 1'b0;
            rst_sync_2 <= 1'b0;
            sync_rst_n <= 1'b0;
        end else begin
            rst_sync_1 <= 1'b1;
            rst_sync_2 <= rst_sync_1;
            sync_rst_n <= rst_sync_2;
        end
    end

endmodule